Experience: 8 + Years
- In-depth knowledge of DFT concepts
- In-depth knowledge and hands-on experience in scan insertion,ATPG, coverage analysis, Transition delay test coverage analysis
- Expertise in test mode timing constraints definition, knowledge in providing timing fixes/corrective actions for timing violations
- Expertise in scripting languages such as Perl, Shell, etc.
- Experience in simulating test vectors
- Knowledge of equivalence check, DFT DRC rules both in RTL lint tool (like spyglass) and ATPG tool like (TK, TetraMax)
- Working experience in Synopsis TetraMax/DFTMax and Cadence Encounter Test is a plus
Job Category: Semiconductor
Job Type: Full Time
Job Location: Bangalore